Voltage peaks or voltage pulses, for example voltage pulses which result from an electrostatic discharge (ESD) or an electrical overstress (EOS), can lead to damage or to reliability problems in semiconductor components or in integrated circuits (ICs) which comprise a plurality of semiconductor components. Voltage peaks may be caused by electrical charge, such as an electrical charge which results from an ESD event. In the case of an ESD event such as this, electrical charge is transmitted in a short time from an object, such as a person or a transmission line, to a circuit node, to which the semiconductor component or the IC is connected. The voltage peak can damage or destroy the semiconductor component or the IC. Damage which occurs as a result of such voltage peaks includes, for example: the interruption of a line connection as a result of the line connection melting, or the destruction or degradation of a gate oxide of a semiconductor component, which is in the form of a MOSFET or IGBT.
Various concepts for overvoltage protection, in particular for ESD protection, are described, for example, in Mergens et al.: “ESD-Protection Considerations in Advanced High-Voltage Technologies for Automotive”, Proceedings of the EOS/ESD Symposium 2006, pages 2A.1-1 to 2A.1-10.
A first known concept provides for a diode which is biased in the reverse direction to be connected in parallel with the semiconductor component to be protected. When a voltage pulse occurs, whose amplitude is higher than the breakdown voltage of the diode, the diode breaks down and dissipates the electrical charge causing the voltage pulse, thus protecting the semiconductor component. However, diodes require a comparatively large semiconductor area.
According to a further known concept, a protection circuit comprises a discharge element, such as a transistor, which is connected in parallel with the semiconductor component to be protected. The protection circuit furthermore comprises a trigger circuit, which triggers the discharge element when a voltage peak is detected whose amplitude is greater than a predetermined threshold voltage. By way of example, a protection circuit such as this is described in U.S. Pat. No. 7,079,369 B2.
Furthermore, so-called GGMOS protection circuits are known (GGMOS=Grounded Gate MOS). Circuits such as these comprise a MOSFET whose drain-source path is connected in parallel with a semiconductor component to be protected, and whose gate is connected to ground or a reference potential. This MOSFET changes to avalanche operation when the voltage across its drain-source path exceeds its avalanche breakdown voltage. The MOSFET therefore prevents any further rise in the voltage across the semiconductor component to be protected. When the MOSFET changes to avalanche operation, a parasitic bipolar transistor is switched on, formed by the drain, source and body regions of the MOSFET. When this parasitic bipolar transistor is switched on, the MOSFET changes to a low-impedance state, the so-called snapback state. In the snapback state, the voltage across the drain-source path is reduced to the value of a holding voltage, which is below the breakdown voltage. In the snapback state, the MOSFET dissipates electrical charge in a very efficient manner. The holding voltage is, however, dependent on the respective design of the MOSFET and the doping concentration of the drain, source and body regions of the MOSFET.
By way of example, further ESD protection circuits are described in U.S. Pat. No. 5,500,546, U.S. Pat. No. 6,958,896 B2, U.S. Pat. No. 7,079,369 B2 and DE 10 297 094 T5. By way of example, overvoltage protection circuits are described in EP 1 783 909 B1 and EP 1 873 917 A1.